As the semiconductor industry has strived for higher device density, higher performance, and lower costs, problems involving both fabrication and design have been encountered. One solution to these problems has been the development of a fin-like field effect transistor (FinFET). A typical FinFET includes a thin vertical ‘fin’ formed by etching spaced recesses into a substrate. The source, drain, and channel regions are defined within this fin. The transistor's gate is wrapped around the channel region of the fin, engaging it on both the top of the fin and the sides of the fin. This configuration allows the gate to induce current flow in the channel from three sides. Thus, FinFET devices have the benefit of higher current flow and reduced short channel effects.
The dimensions of FinFETs and other metal oxide semiconductor field effect transistors (MOSFETs) have been progressively reduced as technological advances have been made in integrated circuit materials. However, this scaling-down trend has slowed due to physical limits of IC materials. Thus, other techniques to increase device performance have been devised. One such technique involves straining the channel region of MOSFET devices to improve electron and hole mobility. Results has been generally adequate, but the level of channel strain obtained thus far has been not entirely satisfactory.
Additionally, there has been a trend in the semiconductor industry to replace the traditional gate oxide and polysilicon gate electrode in FinFET devices with a high-k gate dielectric and metal gate electrode to improve device performance. For example, replacement gate techniques have been devised to fabricate CMOS devices with dual metal gate FinFET devices. However, high costs and burdensome complexity in the fabrication process have rendered dual metal gate devices less than entirely satisfactory.